AMD Helios AI rack targets Nvidia with 72-GPU system

AMD launched the AMD Helios AI rack, its first rack-scale AI platform, with a 72-GPU design built to compete directly with Nvidia’s high-end datacenter systems. The company did not disclose pricing, but says the system will arrive alongside Nvidia’s Vera Rubin generation and deliver a 30 percent performance-per-dollar advantage over competing platforms.

Helios is based on AMD’s new Instinct MI455X accelerator, a CDNA 5 GPU package that combines compute, I/O and HBM4 memory. AMD says the system is larger than Nvidia’s NVL72 rack and, on paper, beats Vera Rubin on several headline measures, including 50 percent more HBM4 and scale-out bandwidth and 15 percent to 25 percent higher AI training performance.

What is AMD Helios?

Helios is a liquid-cooled rack-scale AI system designed to make 72 GPUs operate as a single large compute domain for training and inference. The rack uses the OCP Open Rack Wide form factor, measures 1.2 meters across and is 44OU high, making it substantially wider than Nvidia’s NVL72 design.

The rack contains 18 compute blades, each with four MI455X GPUs. AMD pairs each blade with one 96-core Venice Epyc CPU running at up to 5 GHz, though the company says OEMs and hyperscalers could configure blades with as many as 256 CPU cores.

For its scale-up fabric, AMD is using Ultra Accelerator Link over Ethernet rather than Nvidia’s NVLink. The Helios reference design uses 12 Broadcom Tomahawk 6 switch ASICs across six switch trays, providing 512 lanes of 200 Gbps connectivity and 3.6 TB/s of bidirectional bandwidth per MI455X, according to AMD.

Scale-out networking is also a core part of the pitch. Each MI455X is paired with three 800 Gbps AMD Pensando Vulcano network cards, for 2.4 Tbps of scale-out bandwidth per accelerator. Each compute blade also includes a 400 Gbps Pensando Salina DPU for front-end traffic such as management, APIs and storage. AMD says the rack draws 225 kW to 245 kW under load through a rear 50-volt liquid-cooled DC bus bar.

How strong is the MI455X?

The MI455X uses 24 chiplets with 2.5D and 3D packaging. Its eight compute dies are built on TSMC’s 2nm process and sit above two 3nm fabric and cache dies, which include 96 MB of L2 cache each and the memory controllers for 12 HBM4 stacks of 36 GB apiece. Two separate 3nm I/O dies handle chip-to-chip communication.

AMD says the GPU can operate as one large device or as two smaller NUMA domains, and it supports spatial partitioning into as many as eight virtual GPUs. Compared with the MI355X, AMD claims up to four times higher floating-point performance for AI workloads. The MI455X drops FP64 support to use more die area for AI-focused data types such as MXFP4 and MXFP8, while a separate HPC SKU will serve FP64 workloads.

AMD fellow Alan Smith said the new L2 cache design gives the chip more bandwidth and a simpler data path than the previous generation. According to Smith, one MI455X L2 cache delivers 1.5 times the aggregate bandwidth of the MI355X Infinity cache.

Can Helios match its peak FLOPS claims?

Peak FLOPS figures remain theoretical ceilings, since actual accelerator performance depends on power, thermals, workload shape and software efficiency. Anush Elangovan, AMD’s vice president of AI software, said the MI455X reached 20 petaFLOPS of FP4 performance in real-world testing, about half of its peak figure, while still claiming it is ahead of other accelerators he has seen.

AMD says major customers already include Meta, Microsoft and Oracle. OpenAI has committed to deploy gigawatts of MI455X GPUs in exchange for a roughly 10 percent AMD stake, while Anthropic plans to deploy two gigawatts of the chips tied to an investment of up to $5 billion.

AMD is also preparing other CDNA 5 GPUs. The MI440X is planned for more conventional eight-GPU enterprise systems, while the MI430X is aimed at HPC and scientific computing with FP32 and FP64 support. AMD says MI430X has already been selected for EuroHPC’s Alice Recoque system and Oak Ridge National Laboratory’s Discovery supercomputer, expected in 2027 and 2028 respectively.

This story draws on original reporting from The Register.