Nvidia Vera chip design push adds Cadence, Synopsys and AI agents

Nvidia Vera chip design work is moving from roadmap talk into its own engineering stack: the company said it is running key electronic design automation software for future GPUs on Vera CPUs, with Cadence and Synopsys optimizing tools for the processor. Nvidia said early tests showed 1.5x performance gains for Cadence Jasper and Synopsys VCS, two applications used in verification and simulation before a chip reaches fabrication.

The announcements, made at the 2026 Design Automation Conference in Long Beach, California, extend Nvidia’s pitch that its current silicon can help build its next silicon. The company did not disclose pricing, customer commitments or production deployment timelines for the Vera EDA optimizations.

How is Nvidia using Vera CPUs for chip design?

Nvidia said Vera CPUs are being tuned for CPU-heavy parts of chip development, including logic simulation, formal verification and some digital implementation tasks. Those jobs depend on fast CPU cores, memory efficiency and throughput, even in an industry where Nvidia has spent years arguing for GPU acceleration.

Cadence Jasper is a formal verification platform used to find bugs and validate design behavior. Synopsys VCS is a logic simulation tool used to test complex chip designs before manufacturing. Nvidia said both ran 1.5x faster on Vera CPUs in its early testing, a useful number if it holds across broader production workloads, since verification and simulation consume large amounts of compute during semiconductor development.

Nvidia said it will continue working with Cadence and Synopsys on other EDA workloads for Vera. One stated goal is to help design Rosa, Vera’s successor, which Nvidia said will use its next-generation Rigel core.

AI agents get access to physics and solver libraries

Nvidia also said it is adding PhysicsNeMo and CUDA-X libraries to the Nvidia Agent Toolkit, allowing AI agents to call accelerated solvers as external tools. The company’s claim is that agents can use those libraries to run simulations, reason over physics-related constraints and produce high-fidelity data during chip and system design.

PhysicsNeMo gives developers libraries for training and deploying physics-based AI models. CUDA-X adds accelerated solvers and quantum chemistry capabilities. Nvidia said it is also updating CUDA-X with support for iterative sparse solvers on GPUs, a class of sparse linear algebra used in simulations involving fluid flow, structural stress and electromagnetics.

The new libraries include cuISS for iterative solvers, cuDSS for direct sparse solvers used in circuit and device simulation, and cuEST for quantum chemistry simulations aimed at predicting material behavior at atomic scales.

What performance claims did partners report?

Nvidia cited several partner results, all framed as performance claims from the companies involved. Keysight Technologies said the cuDSS libraries helped accelerate electromagnetic simulations by up to 10x. Silvaco Group said it completed a 3.2 billion-mesh-node photonic edge coupler simulation in under four hours on a 32-GPU cluster. Nvidia said a CPU-based simulation would not match that result.

Cadence’s AuraStack AI Super Agent, which is designed for printed circuit board and advanced packaging workloads, now runs on cuDSS on Nvidia’s Millennium M2000 supercomputer. Cadence said that change improved design verification workflows by 15x. Nvidia noted that verification workloads across chip design consume billions of compute hours annually, making even partial gains commercially meaningful if they transfer outside benchmark settings.

Nvidia said PhysicsNeMo is available under the Apache 2.0 license, while the CUDA-X libraries are free drop-in replacements for code engineers would otherwise write themselves. The free distribution has a clear hardware angle: Nvidia said PhysicsNeMo and CUDA-X run on its own silicon, so adoption of the tools also reinforces demand for Nvidia compute in semiconductor design workflows.

This story draws on original reporting from SiliconANGLE.